In general, semiconductor memory devices may be categorized as either volatile or nonvolatile memory devices. While the volatile memory devices lose their stored data when power is interrupted, the nonvolatile memory devices retain their stored data even when power is interrupted. Volatile memory devices include dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. A unit cell of the SRAM devices may include a flip flop circuit (e.g., two cross-coupled inverters) and two switching elements. Thus, the SRAM cells may stably store their data as long as power is supplied. Meanwhile, a unit cell of the DRAM devices may include a cell transistor acing as a switching element and a cell capacitor acting as a data storage element. If the cell transistor is turned on, the cell capacitor will be charged through the cell transistor to store a data bit in the capacitor.
In the DRAM devices, leakage currents may occur through the cell transistors even though the cell transistors are turned off. Thus, the data (e.g., charges) stored in the capacitors may be lost as the time elapses. Thus, the cell capacitors need to be periodically recharged to retain their stored data.
The refresh operation may be categorized as either an auto-refresh operation or a self-refresh operation. The auto-refresh operation may be executed by refresh commands outputted from a memory controller, and the self-refresh operation may be executed by self-refresh signals which are internally generated in the DRAM devices.
The self-refresh operation may be periodically executed according to a refresh cycle time determined in the DRAM devices. The refresh cycle time may be determined by a data retention time corresponding to a maximum time that the cell capacitors can retain minimum charges which is required to read a correct logic data. The data retention time may be influenced by leakage current characteristics of the cell transistors and the leakage current characteristics of the cell transistors may vary according to an internal temperature of the DRAM devices. Thus, the data retention time may be affected by the internal temperature of the DRAM devices.
As leakage currents increase with an increase of the internal temperature of the DRAM devices, the data retention time decreases with the increase of the internal temperature, and vice versa. Thus, a refresh circuit should be designed such that the refresh cycle time varies according to an internal temperature of the DRAM devices. That is, the refresh cycle time should be reduced to ensure successful operations of the DRAM device as the internal temperature of the DRAM device increases. On the other hand, the refresh cycle time should be increased to reduce the power consumption of the DRAM device as the internal temperature of the DRAM device decreases. Conventional DRAM devices include period signal generation circuits to control the refresh cycle time according to the internal temperature thereof.